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| MAX 7000B (R) Programmable Logic Device Data Sheet September 2003, ver. 3.4 Features... High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX(R)) architecture (see Table 1) - Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V MAX 7000A device families - High-density PLDs ranging from 600 to 10,000 usable gates - 3.5-ns pin-to-pin logic delays with counter frequencies in excess of 303.0 MHz Advanced 2.5-V in-system programmability (ISP) - Programs through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability - Enhanced ISP algorithm for faster programming - ISP_Done bit to ensure complete programming - Pull-up resistor on I/O pins during in-system programming - ISP circuitry compliant with IEEE Std. 1532 f For information on in-system programmable 5.0-V MAX 7000S or 3.3-V MAX 7000A devices, see the MAX 7000 Programmable Logic Device Family Data Sheet or the MAX 7000A Programmable Logic Device Family Data Sheet. Table 1. MAX 7000B Device Features Feature Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tFSU (ns) tCO1 (ns) fCNT (MHz) EPM7032B 600 32 2 36 3.5 2.1 1.0 2.4 303.0 EPM7064B 1,250 64 4 68 3.5 2.1 1.0 2.4 303.0 EPM7128B 2,500 128 8 100 4.0 2.5 1.0 2.8 243.9 EPM7256B 5,000 256 16 164 5.0 3.3 1.0 3.3 188.7 EPM7512B 10,000 512 32 212 5.5 3.6 1.0 3.7 163.9 Altera Corporation DS-MAX7000B-3.4 1 MAX 7000B Programmable Logic Device Data Sheet ...and More Features System-level features - MultiVoltTM I/O interface enabling device core to run at 2.5 V, while I/O pins are compatible with 3.3-V, 2.5-V, and 1.8-V logic levels - Programmable power-saving mode for 50% or greater power reduction in each macrocell - Fast input setup times provided by a dedicated path from I/O pin to macrocell registers - Support for advanced I/O standards, including SSTL-2 and SSTL-3, and GTL+ - Bus-hold option on I/O pins - PCI compatible - Bus-friendly architecture including programmable slew-rate control - Open-drain output option - Programmable security bit for protection of proprietary designs - Built-in boundary-scan test circuitry compliant with IEEE Std. 1149.1 - Supports hot-socketing operation - Programmable ground pins Advanced architecture features - Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance - Configurable expander product-term distribution, allowing up to 32 product terms per macrocell - Programmable macrocell registers with individual clear, preset, clock, and clock enable controls - Two global clock signals with optional inversion - Programmable power-up states for macrocell registers - 6 to 10 pin- or logic-driven output enable signals Advanced package options - Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space-saving FineLine BGATM, 0.8-mm Ultra FineLine BGA, and plastic J-lead chip carrier (PLCC) packages - Pin-compatibility with other MAX 7000B devices in the same package Advanced software support - Software design support and automatic place-and-route provided by Altera's MAX+PLUS(R) II development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations 2 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet - - Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPMs), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Programming support with Altera's Master Programming Unit (MPU), MasterBlasterTM serial/universal serial bus (USB) communications cable, and ByteBlasterMVTM parallel port download cable, as well as programming hardware from thirdparty manufacturers and any JamTM STAPL File (.jam), Jam ByteCode File (.jbc), or Serial Vector Format File (.svf)-capable incircuit tester General Description MAX 7000B devices are high-density, high-performance devices based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000B devices operate with a 2.5-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 3.5 ns, and counter speeds up to 303.0 MHz. See Table 2. Table 2. MAX 7000B Speed Grades Device -3 EPM7032B EPM7064B EPM7128B EPM7256B EPM7512B Notes: (1) Contact Altera Marketing for up-to-date information on available device speed grades. Note (1) Speed Grade -4 -5 v v -7 v v v v v v v v v v -10 v v v The MAX 7000B architecture supports 100% TTL emulation and highdensity integration of SSI, MSI, and LSI logic functions. It easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000B devices are available in a wide range of packages, including PLCC, BGA, FineLine BGA, 0.8-mm Ultra FineLine BGA, PQFP, TQFP, and TQFP packages. See Table 3. Altera Corporation 3 MAX 7000B Programmable Logic Device Data Sheet Table 3. MAX 7000B Maximum User I/O Pins Device 44-Pin 44-Pin PLCC TQFP 48-Pin TQFP 49-Pin 0.8-mm Ultra FineLine BGA (3) 36 41 41 Note (1) 100Pin TQFP 100-Pin FineLine BGA (4) 144Pin TQFP 169-Pin 208Pin 0.8-mm PQFP Ultra FineLine BGA (3) 256Pin BGA 256-Pin FineLine BGA (4) (2) EPM7032B EPM7064B EPM7128B EPM7256B EPM7512B Notes: (1) (2) (3) 36 36 36 36 36 40 68 84 84 68 84 100 120 120 100 141 141 164 176 212 100 164 212 (4) When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O pins become JTAG pins. Contact Altera for up-to-date information on available device package options. All 0.8-mm Ultra FineLine BGA packages are footprint-compatible via the SameFrameTM pin-out feature. Therefore, designers can design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device migration is fully supported by Altera development tools. See "SameFrame Pin-Outs" on page 14 for more details. All FineLine BGA packages are footprint-compatible via the SameFrame pin-out feature. Therefore, designers can design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device migration is fully supported by Altera development tools. See "SameFrame Pin-Outs" on page 14 for more details. MAX 7000B devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000B architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. MAX 7000B devices contain 32 to 512 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and highspeed parallel expander product terms to provide up to 32 product terms per macrocell. 4 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet MAX 7000B devices provide programmable speed/power optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate up to 50% lower power while adding only a nominal timing delay. MAX 7000B devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. The output drivers of all MAX 7000B devices can be set for 3.3 V, 2.5 V, or 1.8 V and all input pins are 3.3-V, 2.5-V, and 1.8-V tolerant, allowing MAX 7000B devices to be used in mixed-voltage systems. MAX 7000B devices are supported by Altera development systems, which are integrated packages that offer schematic, text--including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)-- and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. Altera software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industrystandard PC- and UNIX-workstation-based EDA tools. Altera software runs on Windows-based PCs, as well as Sun SPARCstation, and HP 9000 Series 700/800 workstations. f Functional Description For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet. The MAX 7000B architecture includes the following elements: LABs Macrocells Expander product terms (shareable and parallel) PIA I/O control blocks The MAX 7000B architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of MAX 7000B devices. Altera Corporation 5 MAX 7000B Programmable Logic Device Data Sheet Figure 1. MAX 7000B Device Block Diagram INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 INPUT/GCLRn 6 or 10 Output Enables (1) LAB A 36 36 6 or 10 Output Enables (1) LAB B 2 to 16 2 to 16 2 to 16 I/O 2 to 16 I/O Control Block Macrocells 1 to 16 16 Macrocells 17 to 32 2 to 16 I/O Control Block 2 to 16 I/O 16 6 or 10 2 to 16 2 to 16 2 to 16 6 or 10 LAB C PIA Macrocells 33 to 48 16 36 36 LAB D 2 to 16 2 to 16 I/O I/O Control Block 2 to 16 Macrocells 49 to 64 2 to 16 I/O Control Block 2 to 16 I/O 16 6 or 10 2 to 16 2 to 16 6 or 10 Note: (1) EPM7032B, EPM7064B, EPM7128B, and EPM7256B devices have six output enables. EPM7512B devices have ten output enables. Logic Array Blocks The MAX 7000B device architecture is based on the linking of high-performance LABs. LABs consist of 16 macrocell arrays, as shown in Figure 1. Multiple LABs are linked together via the PIA, a global bus that is fed by all dedicated input pins, I/O pins, and macrocells. Each LAB is fed by the following signals: 36 signals from the PIA that are used for general logic inputs Global controls that are used for secondary register functions Direct input paths from I/O pins to the registers that are used for fast setup times 6 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Macrocells The MAX 7000B macrocell can be individually configured for either sequential or combinatorial logic operation. The macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register. Figure 2 shows the MAX 7000B macrocell. Figure 2. MAX 7000B Macrocell LAB Local Array Global Clear Parallel Logic Expanders (from other macrocells) Global Clocks 2 From I/O pin Fast Input Select Programmable Register Register Bypass To I/O Control Block PRN D/T Q ProductTerm Select Matrix VCC Clock/ Enable Select ENA CLRN Clear Select Shared Logic Expanders 36 Signals from PIA 16 Expander Product Terms To PIA Combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. The product-term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocell's register preset, clock, and clock enable control functions. Two kinds of expander product terms ("expanders") are available to supplement macrocell logic resources: Shareable expanders, which are inverted product terms that are fed back into the logic array Parallel expanders, which are product terms borrowed from adjacent macrocells Altera Corporation 7 MAX 7000B Programmable Logic Device Data Sheet The Altera development system automatically optimizes product-term allocation according to the logic requirements of the design. For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the MAX+PLUS II software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes: Global clock signal. This mode achieves the fastest clock-to-output performance. Global clock signal enabled by an active-high clock enable. A clock enable is generated by a product term. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. Array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. Two global clock signals are available in MAX 7000B devices. As shown in Figure 1, these global clock signals can be the true or the complement of either of the global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figure 2, the product-term select matrix allocates product terms to control these operations. Although the product-term-driven preset and clear from the register are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active-low dedicated global clear pin (GCLRn). Upon power-up, each register in a MAX 7000B device may be set to either a high or low state. This power-up state is specified at design entry. All MAX 7000B I/O pins have a fast input path to a macrocell register. This dedicated path allows a signal to bypass the PIA and combinatorial logic and be clocked to an input D flipflop with an extremely fast input setup time. The input path from the I/O pin to the register has a programmable delay element that can be selected to either guarantee zero hold time or to get the fastest possible set-up time (as fast as 1.0 ns). 8 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, more complex logic functions require additional product terms. Another macrocell can be used to supply the required logic resources. However, the MAX 7000B architecture also offers both shareable and parallel expander product terms ("expanders") that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. A small delay (tSEXP) is incurred when shareable expanders are used. Figure 3 shows how shareable expanders can feed multiple macrocells. Figure 3. MAX 7000B Shareable Expanders Shareable expanders can be shared by any or all macrocells in an LAB. Macrocell Product-Term Logic Product-Term Select Matrix Macrocell Product-Term Logic 36 Signals from PIA 16 Shared Expanders Altera Corporation 9 MAX 7000B Programmable Logic Device Data Sheet Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. The Altera Compiler can automatically allocate up to three sets of up to five parallel expanders to the macrocells that require additional product terms. Each set of five parallel expanders incurs a small, incremental timing delay (tPEXP). For example, if a macrocell requires 14 product terms, the Compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms and the second set includes four product terms, increasing the total delay by 2 x tPEXP. Two groups of eight macrocells within each LAB (e.g., macrocells 1 through 8, and 9 through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lowernumbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of eight, the lowest-numbered macrocell can only lend parallel expanders and the highest-numbered macrocell can only borrow them. Figure 4 shows how parallel expanders can be borrowed from a neighboring macrocell. 10 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Figure 4. MAX 7000B Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. From Previous Macrocell Preset ProductTerm Select Matrix Clock Clear Macrocell ProductTerm Logic Preset ProductTerm Select Matrix Clock Clear Macrocell ProductTerm Logic 36 Signals from PIA 16 Shared Expanders To Next Macrocell Programmable Interconnect Array Logic is routed between LABs on the PIA. This global bus is a programmable path that connects any signal source to any destination on the device. All MAX 7000B dedicated inputs, I/O pins, and macrocell outputs feed the PIA, which makes the signals available throughout the entire device. Only the signals required by each LAB are actually routed from the PIA into the LAB. Figure 5 shows how the PIA signals are routed into the LAB. An EEPROM cell controls one input to a two-input AND gate, which selects a PIA signal to drive into the LAB. Altera Corporation 11 MAX 7000B Programmable Logic Device Data Sheet Figure 5. MAX 7000B PIA Routing To LAB PIA Signals While the routing delays of channel-based routing schemes in masked or field-programmable gate arrays (FPGAs) are cumulative, variable, and path-dependent, the MAX 7000B PIA has a predictable delay. The PIA makes a design's timing performance easy to predict. I/O Control Blocks The I/O control block allows each I/O pin to be individually configured for input, output, or bidirectional operation. All I/O pins have a tri-state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or VCC. Figure 6 shows the I/O control block for MAX 7000B devices. The I/O control block has six or ten global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins, or a subset of the I/O macrocells. 12 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Figure 6. I/O Control Block of MAX 7000B Devices 6 or 10 Global Output Enable Signals (1) PIA OE Select Multiplexer VCC to Other I/O Pins from Macrocell GND Programmable Pull-up Open-Drain Output Slew-Rate Control I/O Standards Programmable Delay Bus Hold Programmable Ground Fast Input to Macrocell Register to PIA Note: (1) EPM7032B, EPM7064B, EPM7128B, and EPM7256B devices have six output enable signals. EPM7512B devices have ten output enable signals. When the tri-state buffer control is connected to ground, the output is tri-stated (high impedance) and the I/O pin can be used as a dedicated input. When the tri-state buffer control is connected to VCC, the output is enabled. The MAX 7000B architecture provides dual I/O feedback, in which macrocell and pin feedbacks are independent. When an I/O pin is configured as an input, the associated macrocell can be used for buried logic. Altera Corporation 13 MAX 7000B Programmable Logic Device Data Sheet SameFrame Pin-Outs MAX 7000B devices support the SameFrame pin-out feature for FineLine BGA and 0.8-mm Ultra FineLine BGA packages. The SameFrame pin-out feature is the arrangement of balls on FineLine BGA and 0.8-mm Ultra FineLine BGA packages such that the lower-ball-count packages form a subset of the higher-ball-count packages. SameFrame pin-outs provide the flexibility to migrate not only from device to device within the same package, but also from one package to another. FineLine BGA packages are compatible with other FineLine BGA packages, and 0.8-mm Ultra FineLine BGA packages are compatible with other 0.8-mm Ultra FineLine BGA packages. A given printed circuit board (PCB) layout can support multiple device density/package combinations. For example, a single board layout can support a range of devices from an EPM7064B device in a 100-pin FineLine BGA package to an EPM7512B device in a 256-pin FineLine BGA package. The Altera software provides support to design PCBs with SameFrame pin-out devices. Devices can be defined for present and future use. The Altera software generates pin-outs describing how to layout a board to take advantage of this migration (see Figure 7). Figure 7. SameFrame Pin-Out Example Printed Circuit Board Designed for 256-Pin FineLine BGA Package 100-Pin FineLine BGA 256-Pin FineLine BGA 100-Pin FineLine BGA Package (Reduced I/O Count or Logic Requirements) 256-Pin FineLine BGA Package (Increased I/O Count or Logic Requirements) 14 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet In-System Programmability (ISP) MAX 7000B devices can be programmed in-system via an industrystandard 4-pin IEEE Std. 1149.1 (JTAG) interface. ISP offers quick, efficient iterations during design development and debugging cycles. The MAX 7000B architecture internally generates the high programming voltages required to program EEPROM cells, allowing in-system programming with only a single 2.5-V power supply. During in-system programming, the I/O pins are tri-stated and weakly pulled-up to eliminate board conflicts. The pull-up value is nominally 50 k3/4. MAX 7000B devices have an enhanced ISP algorithm for faster programming. These devices also offer an ISP_Done bit that provides safe operation when in-system programming is interrupted. This ISP_Done bit, which is the last bit programmed, prevents all I/O pins from driving until the bit is programmed. ISP simplifies the manufacturing flow by allowing devices to be mounted on a PCB with standard pick-and-place equipment before they are programmed. MAX 7000B devices can be programmed by downloading the information via in-circuit testers, embedded processors, the Altera MasterBlaster communications cable, and the ByteBlasterMV parallel port download cable. Programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., QFP packages) due to device handling. MAX 7000B devices can be reprogrammed after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem. In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. A constant algorithm uses a pre-defined (non-adaptive) programming sequence that does not take advantage of adaptive algorithm programming time improvements. Some in-circuit testers cannot program using an adaptive algorithm. Therefore, a constant algorithm must be used. MAX 7000B devices can be programmed with either an adaptive or constant (non-adaptive) algorithm. The Jam Standard Test and Programming Language (STAPL), JEDEC standard JESD-71, can be used to program MAX 7000B devices with in-circuit testers, PCs, or embedded processors. f For more information on using the Jam language, see Application Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor) and Application Note 122 (Using STAPL for ISP & ICR via an Embedded Processor). The ISP circuitry in MAX 7000B devices is compliant with the IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors. Altera Corporation 15 MAX 7000B Programmable Logic Device Data Sheet Programming Sequence During in-system programming, instructions, addresses, and data are shifted into the MAX 7000B device through the TDI input pin. Data is shifted out through the TDO output pin and compared against the expected data. Programming a pattern into the device requires the following six ISP stages. A stand-alone verification of a programmed pattern involves only stages 1, 2, 5, and 6. 1. Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1 ms. Check ID. Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time. Bulk Erase. Erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100 ms. Program. Programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells. This process is repeated for each EEPROM address. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address. Exit ISP. An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. The exit ISP stage requires 1 ms. 2. 3. 4. 5. 6. Programming Times The time required to implement each of the six programming stages can be broken into the following two elements: A pulse time to erase, program, or read the EEPROM cells. A shifting time based on the test clock (TCK) frequency and the number of TCK cycles to shift instructions, address, and data into the device. 16 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet By combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the TCK frequency, the number of devices, and specific target device(s). Because different ISP-capable devices have a different number of EEPROM cells, both the total fixed and total variable times are unique for a single device. Programming a Single MAX 7000B Device The time required to program a single MAX 7000B device in-system can be calculated from the following formula: t PROG =t PPULSE Cycle PTCK + ------------------------------f TCK where: tPROG tPPULSE = Programming time = Sum of the fixed times to erase, program, and verify the EEPROM cells CyclePTCK = Number of TCK cycles to program a device = TCK frequency fTCK The ISP times for a stand-alone verification of a single MAX 7000B device can be calculated from the following formula: Cycle VTCK t VER = t VPULSE + -------------------------------f TCK = Verify time where: tVER = Sum of the fixed times to verify the EEPROM cells tVPULSE CycleVTCK = Number of TCK cycles to verify a device Altera Corporation 17 MAX 7000B Programmable Logic Device Data Sheet The programming times described in Tables 4 through 6 are associated with the worst-case method using the enhanced ISP algorithm. Table 4. MAX 7000B tPULSE & CycleTCK Values Device Programming tPPULSE (s) EMP7032B EMP7064B EMP7128B EMP7256B EMP7512B 2.12 2.12 2.12 2.12 2.12 Stand-Alone Verification tVPULSE (s) 0.002 0.002 0.002 0.002 0.002 CyclePTCK 70,000 120,000 222,000 466,000 914,000 CycleVTCK 18,000 35,000 69,000 151,000 300,000 Tables 5 and 6 show the in-system programming and stand alone verification times for several common test clock frequencies. Table 5. MAX 7000B In-System Programming Times for Different Test Clock Frequencies Device 10 MHz EMP7032B EMP7064B EMP7128B EMP7256B EMP7512B 2.13 2.13 2.14 2.17 2.21 fTCK 5 MHz 2.13 2.14 2.16 2.21 2.30 Units 200 kHz 2.47 2.72 3.23 4.45 6.69 2 MHz 2.15 2.18 2.23 2.35 2.58 1 MHz 2.19 2.24 2.34 2.58 3.03 500 kHz 2.26 2.36 2.56 3.05 3.95 100 kHz 2.82 3.32 4.34 6.78 11.26 50 kHz 3.52 4.52 6.56 11.44 20.40 s s s s s Table 1. MAX 7000B Stand-Alone Verification Times for Different Test Clock Frequencies Device 10 MHz EMP7032B EMP7064B EMP7128B EMP7256B EMP7512B 0.00 0.01 0.01 0.02 0.03 fTCK 5 MHz 0.01 0.01 0.02 0.03 0.06 Units 200 kHz 0.09 0.18 0.35 0.76 1.50 2 MHz 0.01 0.02 0.04 0.08 0.15 1 MHz 0.02 0.04 0.07 0.15 0.30 500 kHz 0.04 0.07 0.14 0.30 0.60 100 kHz 0.18 0.35 0.69 1.51 3.00 50 kHz 0.36 0.70 1.38 3.02 6.00 s s s s s 18 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Programming with External Hardware f MAX 7000B devices can be programmed on Windows-based PCs with an Altera Logic Programmer card, the Master Programming Unit (MPU), and the appropriate device adapter. The MPU performs continuity checking to ensure adequate electrical contact between the adapter and the device. For more information, see the Altera Programming Hardware Data Sheet. The Altera software can use text- or waveform-format test vectors created with the Altera Text Editor or Waveform Editor to test the programmed device. For added design verification, designers can perform functional testing to compare the functional device behavior with the results of simulation. Data I/O, BP Microsystems, and other programming hardware manufacturers provide programming support for Altera devices. For more information, see Programming Hardware Manufacturers. IEEE Std. 1149.1 (JTAG) Boundary-Scan Support MAX 7000B devices include the JTAG boundary-scan test circuitry defined by IEEE Std. 1149.1. Table 6 describes the JTAG instructions supported by MAX 7000B devices. The pin-out tables starting on page 59 of this data sheet show the location of the JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are available as user I/O pins. Table 6. MAX 7000B JTAG Instructions JTAG Instruction SAMPLE/PRELOAD EXTEST BYPASS Description Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the boundary-scan test data to pass synchronously through a selected device to adjacent devices during normal operation. Allows the values in the boundary-scan register to determine pin states while placing the 1-bit bypass register between the TDI and TDO pins. Selects the IDCODE register and places it between the TDI and TDO pins, allowing the IDCODE to be serially shifted out of TDO. Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE value to be shifted out of TDO. These instructions are used when programming MAX 7000B devices via the JTAG ports with the MasterBlaster or ByteBlasterMV download cable, or using a Jam File (.jam), Jam Byte-Code File (.jbc), or Serial Vector Format File (.svf) via an embedded processor or test equipment. CLAMP IDCODE USERCODE ISP Instructions Altera Corporation 19 MAX 7000B Programmable Logic Device Data Sheet The instruction register length of MAX 7000B devices is ten bits. The MAX 7000B USERCODE register length is 32 bits. Tables 7 and 8 show the boundary-scan register length and device IDCODE information for MAX 7000B devices. Table 7. MAX 7000B Boundary-Scan Register Length Device EPM7032B EPM7064B EPM7128B EPM7256B EPM7512B Boundary-Scan Register Length 96 192 288 480 624 Table 8. 32-Bit MAX 7000B Device IDCODE Device Version (4 Bits) EPM7032B EPM7064B EPM7128B EPM7256B EPM7512B Notes: (1) (2) Note (1) IDCODE (32 Bits) Part Number (16 Bits) 0111 0000 0011 0010 0111 0000 0110 0100 0111 0001 0010 1000 0111 0010 0101 0110 0111 0101 0001 0010 Manufacturer's 1 (1 Bit) Identity (11 Bits) (2) 00001101110 00001101110 00001101110 00001101110 00001101110 1 1 1 1 1 0010 0010 0010 0010 0010 The most significant bit (MSB) is on the left. The least significant bit (LSB) for all JTAG IDCODEs is 1. f See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) for more information on JTAG boundary-scan testing. Figure 8 shows the timing information for the JTAG signals. 20 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Figure 8. MAX 7000B JTAG Waveforms TMS TDI t JCP t JCH TCK tJPZX TDO tJSSU Signal to Be Captured Signal to Be Driven tJSH t JPCO t JPXZ t JCL t JPSU t JPH tJSZX tJSCO tJSXZ Table 9 shows the JTAG timing parameters and values for MAX 7000B devices. Table 9. JTAG Timing Parameters & Values for MAX 7000B Devices Note (1) Symbol tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance 20 45 25 25 25 Parameter Min 100 50 50 20 45 Max Unit ns ns ns ns ns 25 25 25 ns ns ns ns ns ns ns ns Note: (1) Timing parameters in this table apply to all VCCIO levels. Altera Corporation 21 MAX 7000B Programmable Logic Device Data Sheet Programmable Speed/Power Control MAX 7000B devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. This feature allows total power dissipation to be reduced by 50% or more, because most logic applications require only a small fraction of all gates to operate at maximum frequency. The designer can program each individual macrocell in a MAX 7000B device for either high-speed or low-power operation. As a result, speedcritical paths in the design can run at high speed, while the remaining paths can operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC, tACL, tCPPW, tEN, and tSEXP parameters. Output Configuration MAX 7000B device outputs can be programmed to meet a variety of system-level requirements. MultiVolt I/O Interface The MAX 7000B device architecture supports the MultiVolt I/O interface feature, which allows MAX 7000B devices to connect to systems with differing supply voltages. MAX 7000B devices in all packages can be set for 3.3-V, 2.5-V, or 1.8-V pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). The VCCIO pins can be connected to either a 3.3-V, 2.5-V, or 1.8-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 1.8-V power supply, the output levels are compatible with 1.8-V systems. When the VCCIO pins are connected to a 2.5-V power supply, the output levels are compatible with 2.5-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is at 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels of 2.5 V or 1.8 V incur a nominal timing delay adder. Table 10 describes the MAX 7000B MultiVolt I/O support. 22 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Table 10. MAX 7000B MultiVolt I/O Support VCCIO (V) 1.8 1.8 2.5 3.3 Input Signal (V) 2.5 v v v 3.3 v v v 5.0 1.8 v v v v Output Signal (V) 2.5 v v v 3.3 5.0 Open-Drain Output Option MAX 7000B devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired-OR plane. Programmable Ground Pins Each unused I/O pin on MAX 7000B devices may be used as an additional ground pin. This programmable ground feature does not require the use of the associated macrocell; therefore, the buried macrocell is still available for user logic. Slew-Rate Control The output buffer for each MAX 7000B I/O pin has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. When the configuration cell is turned off, the slew rate is set for low-noise performance. Each I/O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate on a pin-by-pin basis. The slew rate control affects both the rising and falling edges of the output signal. Advanced I/O Standard Support The MAX 7000B I/O pins support the following I/O standards: LVTTL, LVCMOS, 1.8-V I/O, 2.5-V I/O, GTL+, SSTL-3 Class I and II, and SSTL-2 Class I and II. Altera Corporation 23 MAX 7000B Programmable Logic Device Data Sheet MAX 7000B devices contain two I/O banks. Both banks support all standards. Each I/O bank has its own VCCIO pins. A single device can support 1.8-V, 2.5-V, and 3.3-V interfaces; each bank can support a different standard independently. Within a bank, any one of the terminated standards can be supported. Figure 9 shows the arrangement of the MAX 7000B I/O banks. Figure 9. MAX 7000B I/O Banks for Various Advanced I/O Standards Programmable I/O Banks Individual Power Bus Table 11 shows which macrocells have pins in each I/O bank. Table 11. Macrocell Pins Contained in Each I/O Bank Device EPM7032B EPM7064B EPM7128B EPM7256B EPM7512B Bank 1 1-16 1-32 1-64 1-128, 177-181 1-265 Bank 2 17-32 33-64 65-128 129-176, 182-256 266-512 Each MAX 7000B device has two VREF pins. Each can be set to a separate VREF level. Any I/O pin that uses one of the voltage-referenced standards (GTL+, SSTL-2, or SSTL-3) may use either of the two VREF pins. If these pins are not required as VREF pins, they may be individually programmed to function as user I/O pins. 24 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Programmable Pull-Up Resistor Each MAX 7000B device I/O pin provides an optional programmable pull-up resistor during user mode. When this feature is enabled for an I/O pin, the pull-up resistor (typically 50 k3/4) weakly holds the output to VCCIO level. Bus Hold Each MAX 7000B device I/O pin provides an optional bus-hold feature. When this feature is enabled for an I/O pin, the bus-hold circuitry weakly holds the signal at its last driven state. By holding the last driven state of the pin until the next input signals is present, the bus-hold feature can eliminate the need to add external pull-up or pull-down resistors to hold a signal level when the bus is tri-stated. The bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. This feature can be selected individually for each I/O pin. The bus-hold output will drive no higher than VCCIO to prevent overdriving signals. The propagation delays through the input and output buffers in MAX 7000B devices are not affected by whether the bus-hold feature is enabled or disabled. The bus-hold circuitry weakly pulls the signal level to the last driven state through a resistor with a nominal resistance (RBH) of approximately 8.5 k3/4. Table 12 gives specific sustaining current that will be driven through this resistor and overdrive current that will identify the next driven input level. This information is provided for each VCCIO voltage level. Table 12. Bus Hold Parameters Parameter Conditions 1.8 V Min Low sustaining current High sustaining current Low overdrive current High overdrive current VIN > VIL (max) VIN < VIH (min) 0 V < VIN < VCCIO 0 V < VIN < VCCIO 30 -30 200 -295 VCCIO Level 2.5 V Min 50 -50 300 -435 Units 3.3 V Min 70 -70 500 -680 Max Max Max A A A A The bus-hold circuitry is active only during user operation. At power-up, the bus-hold circuit initializes its initial hold value as VCC approaches the recommended operation conditions. When transitioning from ISP to User Mode with bus hold enabled, the bus-hold circuit captures the value present on the pin at the end of programming. Altera Corporation 25 MAX 7000B Programmable Logic Device Data Sheet Two inverters implement the bus-hold circuitry in a loop that weakly drives back to the I/O pin in user mode. Figure 10 shows a block diagram of the bus-hold circuit. Figure 10. Bus-Hold Circuit Bus Hold Circuit Drive to VCCIO level RBH I/O PCI Compatibility MAX 7000B devices are compatible with PCI applications as well as all 3.3-V electrical specifications in the PCI Local Bus Specification Revision 2.2 except for the clamp diode. While having multiple clamp diodes on a signal trace may be redundant, designers can add an external clamp diode to meet the specification. Table 13 shows the MAX 7000B device speed grades that meet the PCI timing specifications. Table 13. MAX 7000B Device Speed Grades that Meet PCI Timing Specifications Device 33-MHz PCI EPM7032B EPM7064B EPM7128B EPM7256B EPM7512B Note: (1) The EPM7256B and EPM7512B devices in a -5 speed grade meet all PCI timing specifications for 66-MHz operation except the Input Setup Time to CLK--Bused Signal parameter. However, these devices are within 1 ns of that parameter. EPM7256B and EPM7512B devices meet all other 66-MHz PCI timing specifications. Specification 66-MHz PCI -3 -3 -4 -5 (1) -5 (1) All speed grades All speed grades All speed grades All speed grades All speed grades 26 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Power Sequencing & Hot-Socketing Because MAX 7000B devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. The VCCIO and VCCINT power planes can be powered in any order. Signals can be driven into MAX 7000B devices before and during powerup (and power-down) without damaging the device. Additionally, MAX 7000B devices do not drive out during power-up. Once operating conditions are reached, MAX 7000B devices operate as specified by the user. MAX 7000B device I/O pins will not source or sink more than 300 A of DC current during power-up. All pins can be driven up to 4.1 V during hot-socketing. Design Security All MAX 7000B devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security, because programmed data within EEPROM cells is invisible. The security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. MAX 7000B devices are fully functionally tested. Complete testing of each programmable EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in Figure 11. Test patterns can be used and then erased during early stages of the production flow. Generic Testing Altera Corporation 27 MAX 7000B Programmable Logic Device Data Sheet Figure 11. MAX 7000B AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large-amplitude, fast-groundcurrent transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. Numbers in brackets are for 2.5-V outputs. Numbers without brackets are for 3.3-V outputs. Switches S1 and S2 are open for all tests except output disable timing parameters. VCCIO S1 720 [521 ] Device Output To Test System 600 [481 ] C1 (includes jig capacitance) Device input rise and fall times < 2 ns S2 Operating Conditions Tables 14 through 17 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for MAX 7000B devices. Note (1) Min -0.5 -0.5 (2) Table 14. MAX 7000B Device Absolute Maximum Ratings Symbol VCCINT VCCIO VI IOUT TSTG TA TJ Parameter Supply voltage Supply voltage DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature No bias Under bias Under bias Conditions Max 3.6 3.6 4.6 50 150 135 135 Unit V V V mA C C C -2.0 -33 -65 -65 -65 28 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Table 15. MAX 7000B Device Recommended Operating Conditions Symbol VCCINT VCCIO Parameter Supply voltage for internal logic and (10) input buffers Supply voltage for output drivers, 3.3-V operation Supply voltage for output drivers, 2.5-V operation Supply voltage for output drivers, 1.8-V operation Conditions Min 2.375 3.0 2.375 1.71 2.375 Max 2.625 3.6 2.625 1.89 2.625 3.9 VCCIO 70 85 90 105 40 40 Unit V V V V V V V C C C C ns ns VCCISP VI VO TA Supply voltage during in-system programming Input voltage Output voltage Ambient temperature For commercial use For industrial use (11) (3) -0.5 0 0 -40 0 -40 TJ Junction temperature For commercial use For industrial use (11) tR tF Input rise time Input fall time Altera Corporation 29 MAX 7000B Programmable Logic Device Data Sheet Table 16. MAX 7000B Device DC Operating Conditions Symbol VIH Note (4) Conditions Min 2.0 1.7 0.65 x VCCIO -0.5 -0.5 -0.5 2.4 VCCIO - 0.2 2.1 2.0 1.7 1.2 0.4 0.2 0.2 0.4 0.7 0.4 -10 -10 20 10 10 74 Parameter High-level input voltage for 3.3-V TTL/CMOS High-level input voltage for 2.5-V TTL/CMOS High-level input voltage for 1.8-V TTL/CMOS Max 3.9 3.9 3.9 0.8 0.7 0.35 x VCCIO Unit V V V V V VIL Low-level input voltage for 3.3-V TTL/CMOS and PCI compliance Low-level input voltage for 2.5-V TTL/CMOS Low-level input voltage for 1.8-V TTL/CMOS VOH 3.3-V high-level TTL output voltage IOH = -8 mA DC, VCCIO = 3.00 V (5) 3.3-V high-level CMOS output voltage 2.5-V high-level output voltage IOH = -0.1 mA DC, VCCIO = 3.00 V (5) IOH = -100 A DC, VCCIO = 2.30 V (5) IOH = -1 mA DC, VCCIO = 2.30 V (5) IOH = -2 mA DC, VCCIO = 2.30 V (5) 1.8-V high-level output voltage IOH = -2 mA DC, VCCIO =1.65 V (5) IOL = 8 mA DC, VCCIO = 3.00 V (6) IOL = 0.1 mA DC, VCCIO = 3.00 V (6) IOL = 100 A DC, VCCIO = 2.30 V (6) IOL = 1 mA DC, VCCIO = 2.30 V (6) IOL = 2 mA DC, VCCIO = 2.30 V (6) 1.8-V low-level output voltage IOL = 2 mA DC, VCCIO = 1.7 V (6) VI = -0.5 to 3.9 V (7) VI = -0.5 to 3.9 V (7) VCCIO = 1.7 to 3.6 V (8) V V V V V V V V V V V V VOL 3.3-V low-level TTL output voltage 3.3-V low-level CMOS output voltage 2.5-V low-level output voltage II IOZ RI S P Input leakage current Tri-state output off-state current Value of I/O pin pull-up resistor during in-system programming or during power up A A k3/4 30 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Table 17. MAX 7000B Device Capacitance Symbol CIN CI/O Note (9) Conditions Min Max 8 8 Parameter Input pin capacitance I/O pin capacitance Unit pF pF VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz Notes to tables: See the Operating Requirements for Altera Devices Data Sheet. Minimum DC input voltage is -0.5 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 4.6 V for input currents less than 100 mA and periods shorter than 20 ns. (3) All pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before VCCINT and VCCIO are powered. (4) These values are specified under the Recommended Operating Conditions in Table 15 on page 29. (5) The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers to high-level TTL or CMOS output current. (6) The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to low-level TTL or CMOS output current. (7) This value is specified for normal device operation. During power-up, the maximum leakage current is 300 A. (8) This pull-up exists while devices are being programmed in-system and in unprogrammed devices during power-up. The pull-up resistor is from the pins to VCCIO. (9) Capacitance is measured at 25 C and is sample-tested only. Two of the dedicated input pins (OE1 and GCLRN) have a maximum capacitance of 15 pF. (10) The POR time for all 7000B devices does not exceed 100 s. The sufficient VCCINT voltage level for POR is 2.375 V. The device is fully initialized within the POR time after VCCINT reaches the sufficient POR voltage level. (11) These devices support in-system programming for -40 to 100 C. For in-system programming support between -40 and 0 C, contact Altera Applications. (1) (2) Altera Corporation 31 MAX 7000B Programmable Logic Device Data Sheet Figure 12 shows the typical output drive characteristics of MAX 7000B devices. Figure 12. Output Drive Characteristics of MAX 7000B Devices 3.3-V VCCIO 150 2.5-V VCCIO IOL 150 IOL 120 120 Typical IO Output Current (mA) 90 VCCINT = 2.5 V VCCIO = 3.0 V Room Temperature Typical IO Output Current (mA) 90 60 60 VCCINT = 2.5 V VCCIO = 2.5 V Room Temperature 30 30 IOH 1 2 3 4 1 2 IOH 3 4 VO Output Voltage (V) VO Output Voltage (V) 1.8-V VCCIO 150 IOL 120 Typical IO Output Current (mA) 90 60 VCCINT = 2.5 V VCCIO = 1.8 V Room Temperature 30 IOH 1 2 3 4 VO Output Voltage (V) 32 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Timing Model MAX 7000B device timing can be analyzed with the Altera software, with a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 13. MAX 7000B devices have predictable internal delays that enable the designer to determine the worst-case timing of any design. The Altera software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for device-wide performance evaluation. Figure 13. MAX 7000B Timing Model Internal Output Enable Delay t IOE Input Delay t IN PIA Delay t PIA Global Control Delay t GLOB Logic Array Delay t LAD Register Control Delay t LAC tIC t EN Shared Expander Delay t SEXP Parallel Expander Delay t PEXP Register Delay t SU tH t PRE t CLR t RD t COMB t FSU t FH Output Delay t OD1 t OD2 t OD3 t XZ t Z X1 t Z X2 t Z X3 I/O Delay tIO Fast Input Delay tFIN tFIN + tFIND The timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. External timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. Figure 14 shows the timing relationship between internal and external delay parameters. f See Application Note 94 (Understanding MAX 7000 Timing) for more information. Altera Corporation 33 MAX 7000B Programmable Logic Device Data Sheet Figure 14. MAX 7000B Switching Waveforms tR & tF < 2 ns. Inputs are driven at 3.0 V for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V. Combinatorial Mode tIN Input Pin tIO I/O Pin tPIA PIA Delay tSEXP Shared Expander Delay tLAC , tLAD Logic Array Input tPEXP Parallel Expander Delay tCOMB Logic Array Output tOD Output Pin Global Clock Mode Global Clock Pin Global Clock at Register tR tIN tCH tGLOB tH tCL tF tSU Data or Enable (Logic Array Output) Array Clock Mode tR Input or I/O Pin tACH tIN tIO tACL tF Clock into PIA Clock into Logic Array Clock at Register Data from Logic Array tPIA tIC tSU tH tRD Register to PIA to Logic Array tPIA tOD tCLR , tPRE tOD tPIA Register Output to Pin 34 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Tables 18 through 32 show MAX 7000B device timing parameters. Table 18. EPM7032B External Timing Parameters Symbol Parameter Conditions -3.5 Min tPD1 tPD2 tSU tH tFSU tFH tFZHSU Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock setup time of fast input with zero hold time Global clock hold time of fast input with zero hold time Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time (2) (2) C1 = 35 pF C1 = 35 pF (2) C1 = 35 pF (2) (2) (2) Notes (1) Speed Grade -5.0 Min Max 5.0 5.0 3.0 0.0 1.0 1.0 2.5 4.5 0.0 1.5 1.0 3.0 Unit -7.5 Min Max 7.5 7.5 ns ns ns ns ns ns ns Max 3.5 3.5 2.1 0.0 1.0 1.0 2.0 tFZHH 0.0 0.0 0.0 ns tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT 1.0 1.5 1.5 0.9 0.2 1.0 1.5 1.5 1.5 2.4 1.0 2.0 2.0 1.3 0.3 3.4 1.0 3.0 3.0 1.9 0.6 5.0 ns ns ns ns ns Array clock to output delay C1 = 35 pF (2) Array clock high time Array clock low time Minimum pulse width for clear and preset Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency (2) (2), (3) (2) (2), (3) 3.6 1.0 2.0 2.0 2.0 5.1 1.0 3.0 3.0 3.0 7.6 ns ns ns ns 3.3 303.0 3.3 303.0 212.8 212.8 4.7 142.9 4.7 142.9 7.0 ns MHz 7.0 ns MHz Altera Corporation 35 MAX 7000B Programmable Logic Device Data Sheet Table 19. EPM7032B Internal Timing Parameters Symbol Parameter Conditions Notes (1) Speed Grade -3.5 Min Max 0.3 0.3 0.9 1.0 1.5 0.4 1.4 1.2 0.1 Unit -7.5 Min Max 0.7 0.7 2.0 1.5 3.2 0.9 3.1 2.6 0.3 1.8 ns ns ns ns ns ns ns ns ns ns -5.0 Min Max 0.5 0.5 1.3 1.5 2.1 0.6 2.0 1.7 0.2 1.2 tIN tIO tFIN tFIND tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Programmable delay adder for fast input Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer enable delay slow slew rate = off VCCIO = 3.3 V Output buffer enable delay slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (2) (4) C1 = 35 pF 0.9 tOD3 C1 = 35 pF 5.9 6.2 6.8 ns tZX1 C1 = 35 pF 1.6 2.2 3.4 ns tZX3 C1 = 35 pF 6.6 7.2 8.4 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA C1 = 5 pF 1.6 0.7 0.4 0.8 1.2 0.5 0.2 1.2 1.2 0.7 1.0 1.0 0.7 1.5 1.1 0.5 0.8 1.2 2.2 1.6 0.9 1.1 1.4 0.6 0.3 1.8 1.7 1.1 1.3 1.3 1.0 2.1 3.4 ns ns ns ns ns 0.9 0.5 2.8 2.6 1.6 1.9 1.9 1.4 3.2 ns ns ns ns ns ns ns ns ns 36 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Table 20. EPM7032B Selectable I/O Standard Timing Adder Delays I/O Standard Parameter -3.5 Min 3.3 V TTL/CMOS Input to (PIA) Input to global clock and clear Input to fast input register All outputs 2.5 V TTL/CMOS Input to PIA Input to global clock and clear Input to fast input register All outputs 1.8 V TTL/CMOS Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-2 Class I Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-2 Class II Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-3 Class I Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-3 Class II Input to PIA Input to global clock and clear Input to fast input register All outputs GTL+ Input to PIA Input to global clock and clear Input to fast input register All outputs Notes (1) Speed Grade -5.0 Min Max 0.0 0.0 0.0 0.0 0.4 0.4 0.3 0.3 0.8 0.8 0.5 1.8 1.9 1.8 1.3 0.0 1.9 1.8 1.3 -0.1 1.8 1.3 1.1 0.0 1.8 1.3 1.1 0.0 2.3 2.3 2.1 0.0 Unit -7.5 Min Max 0.0 0.0 0.0 0.0 0.6 0.6 0.4 0.4 1.1 1.1 0.8 2.6 2.8 2.6 1.9 0.0 2.8 2.6 1.9 -0.2 2.6 1.9 1.7 0.0 2.6 1.9 1.7 0.0 3.4 3.4 3.2 0.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max 0.0 0.0 0.0 0.0 0.3 0.3 0.2 0.2 0.5 0.5 0.4 1.2 1.3 1.2 0.9 0.0 1.3 1.2 0.9 -0.1 1.2 0.9 0.8 0.0 1.2 0.9 0.8 0.0 1.6 1.6 1.5 0.0 Altera Corporation 37 MAX 7000B Programmable Logic Device Data Sheet Table 20. EPM7032B Selectable I/O Standard Timing Adder Delays I/O Standard Parameter -3.5 Min PCI Input to PIA Input to global clock and clear Input to fast input register All outputs Notes to tables: (1) (2) (3) (4) Notes (1) Speed Grade -5.0 Min Max 0.0 0.0 0.0 0.0 Unit -7.5 Min Max 0.0 0.0 0.0 0.0 ns ns ns ns Max 0.0 0.0 0.0 0.0 These values are specified under the Recommended Operating Conditions in Table 15 on page 29. See Figure 14 for more information on switching waveforms. These values are specified for a PIA fan-out of all LABs. Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The tLPA parameter must be added to the tLAD, tLAC, tIC, tACL, tCPPW, tEN, and tSEXP parameters for macrocells running in low-power mode. 38 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Table 21. EPM7064B External Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -3 Min Max 3.5 3.5 2.1 0.0 1.0 1.0 2.0 3.0 0.0 1.0 1.0 2.5 Unit -7 -5 Min Max 5.0 5.0 4.5 0.0 1.5 1.0 3.0 Min Max 7.5 7.5 ns ns ns ns ns ns ns tPD1 tPD2 tSU tH tFSU tFH tFZHSU Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock setup time of fast input with zero hold time Global clock hold time of fast input with zero hold time Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time C1 = 35 pF (2) C1 = 35 pF (2) (2) (2) tFZHH 0.0 0.0 0.0 ns tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT C1 = 35 pF 1.0 1.5 1.5 2.4 1.0 2.0 2.0 1.3 0.3 3.4 1.0 3.0 3.0 1.9 0.6 5.0 ns ns ns ns ns (2) (2) 0.9 0.2 1.0 1.5 1.5 1.5 3.6 Array clock to output delay C1 = 35 pF (2) Array clock high time Array clock low time Minimum pulse width for clear and preset Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency (2) (2), (3) (2) (2), (3) 1.0 2.0 2.0 2.0 5.1 1.0 3.0 3.0 3.0 7.6 ns ns ns ns 3.3 303.0 3.3 303.0 212.8 212.8 4.7 142.9 4.7 142.9 7.0 ns MHz 7.0 ns MHz Altera Corporation 39 MAX 7000B Programmable Logic Device Data Sheet Table 22. EPM7064B Internal Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -3 Min Max 0.3 0.3 0.9 1.0 1.5 0.4 1.4 1.2 0.1 Unit -7 -5 Min Max 0.5 0.5 1.3 1.5 2.1 0.6 2.0 1.7 0.2 1.2 Min Max 0.7 0.7 2.0 1.5 3.2 0.9 3.1 2.6 0.3 1.8 ns ns ns ns ns ns ns ns ns ns tIN tIO tFIN tFIND tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Programmable delay adder for fast input Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer enable delay slow slew rate = off VCCIO = 3.3 V Output buffer enable delay slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (2) (4) C1 = 35 pF 0.9 tOD3 C1 = 35 pF 5.9 6.2 6.8 ns tZX1 C1 = 35 pF 1.6 2.2 3.4 ns tZX3 C1 = 35 pF 6.6 7.2 8.4 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA C1 = 5 pF 1.6 0.7 0.4 0.8 1.2 0.5 0.2 1.2 1.2 0.7 1.0 1.0 0.7 1.5 1.1 0.5 0.8 1.2 2.2 1.6 0.9 1.1 1.4 0.6 0.3 1.8 1.7 1.1 1.3 1.3 1.0 2.1 3.4 ns ns ns ns ns 0.9 0.5 2.8 2.6 1.6 1.9 1.9 1.4 3.2 ns ns ns ns ns ns ns ns ns 40 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Table 23. EPM7064B Selectable I/O Standard Timing Adder Delays (Part 1 of 2) I/O Standard Parameter -3 Min 3.3 V TTL/CMOS Input to PIA Input to global clock and clear Input to fast input register All outputs 2.5 V TTL/CMOS Input to PIA Input to global clock and clear Input to fast input register All outputs 1.8 V TTL/CMOS Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-2 Class I Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-2 Class II Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-3 Class I Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-3 Class II Input to PIA Input to global clock and clear Input to fast input register All outputs GTL+ Input to PIA Input to global clock and clear Input to fast input register All outputs Note (1) Unit -7 Speed Grade -5 Max 0.0 0.0 0.0 0.0 0.3 0.3 0.2 0.2 0.5 0.5 0.4 1.2 1.3 1.2 0.9 0.0 1.3 1.2 0.9 -0.1 1.2 0.9 0.8 0.0 1.2 0.9 0.8 0.0 1.6 1.6 1.5 0.0 Min Max 0.0 0.0 0.0 0.0 0.4 0.4 0.3 0.3 0.7 0.7 0.6 1.7 1.9 1.7 1.3 0.0 1.9 1.7 1.3 -0.1 1.7 1.3 1.1 0.0 1.7 1.3 1.1 0.0 2.3 2.3 2.1 0.0 Min Max 0.0 0.0 0.0 0.0 0.6 0.6 0.4 0.4 1.1 1.1 0.9 2.6 2.8 2.6 1.9 0.0 2.8 2.6 1.9 -0.2 2.6 1.9 1.7 0.0 2.6 1.9 1.7 0.0 3.4 3.4 3.2 0.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Altera Corporation 41 MAX 7000B Programmable Logic Device Data Sheet Table 23. EPM7064B Selectable I/O Standard Timing Adder Delays (Part 2 of 2) I/O Standard Parameter -3 Min PCI Input to PIA Input to global clock and clear Input to fast input register All outputs Notes to tables: (1) (2) (3) (4) Note (1) Unit -7 Speed Grade -5 Max 0.0 0.0 0.0 0.0 Min Max 0.0 0.0 0.0 0.0 Min Max 0.0 0.0 0.0 0.0 ns ns ns ns These values are specified under the Recommended Operating Conditions in Table 15 on page 29. See Figure 14 for more information on switching waveforms. These values are specified for a PIA fan-out of all LABs. Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The tLPA parameter must be added to the tLAD, tLAC, tIC, tACL, tCPPW, tEN, and tSEXP parameters for macrocells running in low-power mode. 42 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Table 24. EPM7128B External Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -4 Min Max 4.0 4.0 2.5 0.0 1.0 1.0 2.0 4.5 0.0 1.5 1.0 3.0 Unit -10 -7 Min Max 7.5 7.5 6.1 0.0 1.5 1.0 3.0 Min Max 10.0 10.0 ns ns ns ns ns ns ns tPD1 tPD2 tSU tH tFSU tFH tFZHSU Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock setup time of fast input with zero hold time Global clock hold time of fast input with zero hold time Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time C1 = 35 pF (2) C1 = 35 pF (2) (2) (2) tFZHH 0.0 0.0 0.0 ns tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT C1 = 35 pF 1.0 1.5 1.5 2.8 1.0 3.0 3.0 2.0 0.7 5.7 1.0 4.0 4.0 2.8 0.9 7.5 ns ns ns ns ns (2) (2) 1.2 0.2 1.0 1.5 1.5 1.5 4.1 Array clock to output delay C1 = 35 pF (2) Array clock high time Array clock low time Minimum pulse width for clear and preset Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency (2) (2), (3) (2) (2), (3) 1.0 3.0 3.0 3.0 8.2 1.0 4.0 4.0 4.0 10.8 ns ns ns ns 4.1 243.9 4.1 243.9 126.6 126.6 7.9 94.3 7.9 94.3 10.6 ns MHz 10.6 ns MHz Altera Corporation 43 MAX 7000B Programmable Logic Device Data Sheet Table 25. EPM7128B Internal Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -4 Min Max 0.3 0.3 1.3 1.0 1.5 0.4 1.6 1.4 0.1 Unit -10 -7 Min Max 0.6 0.6 2.9 1.5 2.8 0.8 2.9 2.6 0.3 1.7 Min Max 0.8 0.8 3.7 1.5 3.8 1.0 3.8 3.4 0.4 2.2 ns ns ns ns ns ns ns ns ns ns tIN tIO tFIN tFIND tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Programmable delay adder for fast input Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer enable delay slow slew rate = off VCCIO = 3.3 V Output buffer enable delay slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (2) (4) C1 = 35 pF 0.9 tOD3 C1 = 35 pF 5.9 6.7 7.2 ns tZX1 C1 = 35 pF 1.8 3.3 4.4 ns tZX3 C1 = 35 pF 6.8 8.3 9.4 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA C1 = 5 pF 1.8 1.0 0.4 0.8 1.2 0.5 0.2 1.4 1.4 1.1 1.0 1.0 1.0 1.5 1.9 0.8 0.9 1.6 3.3 2.6 1.1 0.9 1.6 1.1 0.3 2.8 2.6 2.3 1.9 1.9 2.0 2.8 4.4 ns ns ns ns ns 1.4 0.4 3.6 3.4 3.1 2.6 2.6 2.8 3.8 ns ns ns ns ns ns ns ns ns 44 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Table 26. EPM7128B Selectable I/O Standard Timing Adder Delays (Part 1 of 2) I/O Standard Parameter -4 Min 3.3 V TTL/CMOS Input to PIA Input to global clock and clear Input to fast input register All outputs 2.5 V TTL/CMOS Input to PIA Input to global clock and clear Input to fast input register All outputs 1.8 V TTL/CMOS Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-2 Class I Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-2 Class II Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-3 Class I Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-3 Class II Input to PIA Input to global clock and clear Input to fast input register All outputs GTL+ Input to PIA Input to global clock and clear Input to fast input register All outputs Note (1) Unit -10 Speed Grade -7 Max 0.0 0.0 0.0 0.0 0.3 0.3 0.2 0.2 0.5 0.5 0.4 1.2 1.4 1.2 1.0 0.0 1.4 1.2 1.0 -0.1 1.3 1.0 0.9 0.0 1.3 1.0 0.9 0.0 1.7 1.7 1.6 0.0 Min Max 0.0 0.0 0.0 0.0 0.6 0.6 0.4 0.4 0.9 0.9 0.8 2.3 2.6 2.3 1.9 0.0 2.6 2.3 1.9 -0.2 2.4 1.9 1.7 0.0 2.4 1.9 1.7 0.0 3.2 3.2 3.0 0.0 Min Max 0.0 0.0 0.0 0.0 0.8 0.8 0.5 0.5 1.3 1.3 1.0 3.0 3.5 3.0 2.5 0.0 3.5 3.0 2.5 -0.3 3.3 2.5 2.3 0.0 3.3 2.5 2.3 0.0 4.3 4.3 4.0 0.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Altera Corporation 45 MAX 7000B Programmable Logic Device Data Sheet Table 26. EPM7128B Selectable I/O Standard Timing Adder Delays (Part 2 of 2) I/O Standard Parameter -4 Min PCI Input to PIA Input to global clock and clear Input to fast input register All outputs Notes to tables: (1) (2) (3) (4) Note (1) Unit -10 Speed Grade -7 Max 0.0 0.0 0.0 0.0 Min Max 0.0 0.0 0.0 0.0 Min Max 0.0 0.0 0.0 0.0 ns ns ns ns These values are specified under the Recommended Operating Conditions in Table 15 on page 29. See Figure 14 for more information on switching waveforms. These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The tLPA parameter must be added to the tLAD, tLAC, tIC, tACL, tCPPW, tEN, and tSEXP parameters for macrocells running in low-power mode. 46 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Table 27. EPM7256B External Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -5 Min Max 5.0 5.0 3.3 0.0 1.0 1.0 2.5 4.8 0.0 1.5 1.0 3.0 Unit -10 -7 Min Max 7.5 7.5 6.6 0.0 1.5 1.0 3.0 Min Max 10.0 10.0 ns ns ns ns ns ns ns tPD1 tPD2 tSU tH tFSU tFH tFZHSU Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time for fast input Global clock setup time of fast input with zero hold time Global clock hold time of fast input with zero hold time Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time C1 = 35 pF (2) C1 = 35 pF (2) (2) (2) tFZHH 0.0 0.0 0.0 ns tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT C1 = 35 pF 1.0 2.0 2.0 3.3 1.0 3.0 3.0 2.0 0.8 5.1 1.0 4.0 4.0 2.8 1.0 6.7 ns ns ns ns ns (2) (2) 1.4 0.4 1.0 2.0 2.0 2.0 5.2 Array clock to output delay C1 = 35 pF (2) Array clock high time Array clock low time Minimum pulse width for clear and preset Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency (2) (2), (3) (2) (2), (3) 1.0 3.0 3.0 3.0 7.9 1.0 4.0 4.0 4.0 10.5 ns ns ns ns 5.3 188.7 5.3 188.7 126.6 126.6 7.9 94.3 7.9 94.3 10.6 ns MHz 10.6 ns MHz Altera Corporation 47 MAX 7000B Programmable Logic Device Data Sheet Table 28. EPM7256B Internal Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -5 Min Max 0.4 0.4 1.5 1.5 1.5 0.4 1.7 1.5 0.1 Unit -10 -7 Min Max 0.6 0.6 2.5 1.5 2.3 0.6 2.5 2.2 0.2 1.4 Min Max 0.8 0.8 3.1 1.5 3.0 0.8 3.3 2.9 0.3 1.9 ns ns ns ns ns ns ns ns ns ns tIN tIO tFIN tFIND tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Programmable delay adder for fast input Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer enable delay slow slew rate = off VCCIO = 3.3 V Output buffer enable delay slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (2) (4) C1 = 35 pF 0.9 tOD3 C1 = 35 pF 5.9 6.4 6.9 ns tZX1 C1 = 35 pF 2.2 3.3 4.5 ns tZX3 C1 = 35 pF 7.2 8.3 9.5 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA C1 = 5 pF 2.2 1.2 0.6 0.8 1.2 0.7 0.3 1.5 1.5 1.3 1.0 1.0 1.7 2.0 1.8 1.0 1.1 1.4 3.3 2.5 1.3 1.1 1.4 1.0 0.4 2.3 2.2 2.1 1.6 1.6 2.6 3.0 4.5 ns ns ns ns ns 1.3 0.5 3.0 2.9 2.7 2.1 2.1 3.3 4.0 ns ns ns ns ns ns ns ns ns 48 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Table 29. EPM7256B Selectable I/O Standard Timing Adder Delays (Part 1 of 2) I/O Standard Parameter -5 Min 3.3 V TTL/CMOS Input to PIA Input to global clock and clear Input to fast input register All outputs 2.5 V TTL/CMOS Input to PIA Input to global clock and clear Input to fast input register All outputs 1.8 V TTL/CMOS Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-2 Class I Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-2 Class II Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-3 Class I Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-3 Class II Input to PIA Input to global clock and clear Input to fast input register All outputs GTL+ Input to PIA Input to global clock and clear Input to fast input register All outputs Note (1) Unit -10 Speed Grade -7 Max 0.0 0.0 0.0 0.0 0.4 0.3 0.2 0.2 0.6 0.6 0.5 1.3 1.5 1.3 1.1 0.0 1.5 1.3 1.1 -0.1 1.4 1.1 1.0 0.0 1.4 1.1 1.0 0.0 1.8 1.8 1.7 0.0 Min Max 0.0 0.0 0.0 0.0 0.6 0.5 0.3 0.3 0.9 0.9 0.8 2.0 2.3 2.0 1.7 0.0 2.3 2.0 1.7 -0.2 2.1 1.7 1.5 0.0 2.1 1.7 1.5 0.0 2.7 2.7 2.6 0.0 Min Max 0.0 0.0 0.0 0.0 0.8 0.6 0.4 0.4 1.2 1.2 1.0 2.6 3.0 2.6 2.2 0.0 3.0 2.6 2.2 -0.2 2.8 2.2 2.0 0.0 2.8 2.2 2.0 0.0 3.6 3.6 3.4 0.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Altera Corporation 49 MAX 7000B Programmable Logic Device Data Sheet Table 29. EPM7256B Selectable I/O Standard Timing Adder Delays (Part 2 of 2) I/O Standard Parameter -5 Min PCI Input to PIA Input to global clock and clear Input to fast input register All outputs Notes to tables: (1) (2) (3) (4) Note (1) Unit -10 Speed Grade -7 Max 0.0 0.0 0.0 0.0 Min Max 0.0 0.0 0.0 0.0 Min Max 0.0 0.0 0.0 0.0 ns ns ns ns These values are specified under the Recommended Operating Conditions in Table 15 on page 29. See Figure 14 for more information on switching waveforms. These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The tLPA parameter must be added to the tLAD, tLAC, tIC, tACL, tCPPW, tEN, and tSEXP parameters for macrocells running in low-power mode. 50 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Table 30. EPM7512B External Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -5 Min Max 5.5 5.5 3.6 0.0 1.0 1.0 2.5 4.9 0.0 1.5 1.0 3.0 Unit -10 -7 Min Max 7.5 7.5 6.5 0.0 1.5 1.0 3.0 Min Max 10.0 10.0 ns ns ns ns ns ns ns tPD1 tPD2 tSU tH tFSU tFH tFZHSU Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock setup time of fast input with zero hold time Global clock hold time of fast input with zero hold time Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time C1 = 35 pF (2) C1 = 35 pF (2) (2) (2) tFZHH 0.0 0.0 0.0 ns tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT C1 = 35 pF 1.0 3.0 3.0 3.7 1.0 3.0 3.0 1.9 0.6 5.0 1.0 4.0 4.0 2.5 0.8 6.7 ns ns ns ns ns (2) (2) 1.4 0.5 1.0 3.0 3.0 3.0 5.9 Array clock to output delay C1 = 35 pF (2) Array clock high time Array clock low time Minimum pulse width for clear and preset Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency (2) (2), (3) (2) (2), (3) 1.0 3.0 3.0 3.0 8.0 1.0 4.0 4.0 4.0 10.7 ns ns ns ns 6.1 163.9 6.1 163.9 119.0 119.0 8.4 90.1 8.4 90.1 11.1 ns MHz 11.1 ns MHz Altera Corporation 51 MAX 7000B Programmable Logic Device Data Sheet Table 31. EPM7512B Internal Timing Parameters Symbol Parameter Conditions Note (1) Speed Grade -5 Min Max 0.3 0.3 2.2 1.5 1.5 0.4 1.7 1.5 0.1 Unit -10 -7 Min Max 0.3 0.3 3.2 1.5 2.1 0.5 2.3 2.0 0.2 1.2 Min Max 0.5 0.5 4.0 1.5 2.7 0.7 3.0 2.6 0.2 1.6 ns ns ns ns ns ns ns ns ns ns tIN tIO tFIN tFIND tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Programmable delay adder for fast input Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer enable delay slow slew rate = off VCCIO = 3.3 V Output buffer enable delay slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (2) (4) C1 = 35 pF 0.9 tOD3 C1 = 35 pF 5.9 6.2 6.6 ns tZX1 C1 = 35 pF 2.8 3.8 5.0 ns tZX3 C1 = 35 pF 7.8 8.8 10.0 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA C1 = 5 pF 2.8 1.5 0.4 0.8 1.2 0.5 0.2 1.8 1.5 2.0 1.0 1.0 2.4 2.0 2.0 0.5 1.1 1.4 3.8 2.6 0.7 1.1 1.4 0.7 0.3 2.4 2.0 2.8 1.4 1.4 3.4 2.7 5.0 ns ns ns ns ns 1.0 0.4 3.1 2.6 3.6 1.9 1.9 4.5 3.6 ns ns ns ns ns ns ns ns ns 52 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Table 32. EPM7512B Selectable I/O Standard Timing Adder Delays (Part 1 of 2) I/O Standard Parameter -5 Min 3.3 V TTL/CMOS Input to PIA Input to global clock and clear Input to fast input register All outputs 2.5 V TTL/CMOS Input to PIA Input to global clock and clear Input to fast input register All outputs 1.8 V TTL/CMOS Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-2 Class I Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-2 Class II Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-3 Class I Input to PIA Input to global clock and clear Input to fast input register All outputs SSTL-3 Class II Input to PIA Input to global clock and clear Input to fast input register All outputs GTL+ Input to PIA Input to global clock and clear Input to fast input register All outputs Note (1) Unit -10 Speed Grade -7 Max 0.0 0.0 0.0 0.0 0.4 0.3 0.2 0.2 0.7 0.6 0.5 1.3 1.5 1.4 1.1 0.0 1.5 1.4 1.1 -0.1 1.4 1.2 1.0 0.0 1.4 1.2 1.0 0.0 1.8 1.9 1.8 0.0 Min Max 0.0 0.0 0.0 0.0 0.5 0.4 0.3 0.3 1.0 0.8 0.6 1.8 2.0 1.9 1.5 0.0 2.0 1.9 1.5 -0.1 1.9 1.6 1.4 0.0 1.9 1.6 1.4 0.0 2.5 2.6 2.5 0.0 Min Max 0.0 0.0 0.0 0.0 0.7 0.5 0.3 0.3 1.3 1.0 0.8 2.3 2.7 2.5 2.0 0.0 2.7 2.5 2.0 -0.2 2.5 2.2 1.8 0.0 2.5 2.2 1.8 0.0 3.3 3.5 3.3 0.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Altera Corporation 53 MAX 7000B Programmable Logic Device Data Sheet Table 32. EPM7512B Selectable I/O Standard Timing Adder Delays (Part 2 of 2) I/O Standard Parameter -5 Min PCI Input to PIA Input to global clock and clear Input to fast input register All outputs Notes to tables: (1) (2) (3) (4) Note (1) Unit -10 Speed Grade -7 Max 0.0 0.0 0.0 0.0 Min Max 0.0 0.0 0.0 0.0 Min Max 0.0 0.0 0.0 0.0 ns ns ns ns These values are specified under the Recommended Operating Conditions in Table 15 on page 29. See Figure 14 for more information on switching waveforms. These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.12 ns to the PIA timing value. Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. The tLPA parameter must be added to the tLAD, tLAC, tIC, tACL, tCPPW, tEN, and tSEXP parameters for macrocells running in low-power mode. Power Consumption Supply power (P) versus frequency (fMAX, in MHz) for MAX 7000B devices is calculated with the following equation: P = PINT + PIO = ICCINT x VCC + PIO The PIO value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices). 54 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet The ICCINT value depends on the switching frequency and the application logic. The ICCINT value is calculated with the following equation: ICCINT = (A x MCTON) + [B x (MCDEV - MCTON)] + (C x MCUSED x fMAX x togLC) The parameters in this equation are: MCTON MCDEV MCUSED fMAX togLC A, B, C = Number of macrocells with the Turbo BitTM option turned on, as reported in the MAX+PLUS II Report File (.rpt) = Number of macrocells in the device = Total number of macrocells in the design, as reported in the Report File = Highest clock frequency to the device = Average percentage of logic cells toggling at each clock (typically 12.5%) = Constants, shown in Table 33 Table 33. MAX 7000B ICC Equation Constants Device EPM7032B EPM7064B EPM7128B EPM7256B EPM7512B A 0.91 0.91 0.91 0.91 0.91 B 0.54 0.54 0.54 0.54 0.54 C 0.010 0.012 0.016 0.017 0.019 This calculation provides an ICC estimate based on typical conditions using a pattern of a 16-bit, loadable, enabled, up/down counter in each LAB with no output load. Actual ICC should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. Altera Corporation 55 MAX 7000B Programmable Logic Device Data Sheet Figure 15. ICC vs. Frequency for EPM7032B Devices 45 EPM7032B VCC = 2.5 V Room Temperature 285.7 MHz 40 35 High Speed 30 Typical ICC 25 Active (mA) 20 15 153.8 MHz Low Power 10 5 0 50 100 150 Frequency (MHz) 200 250 300 Figure 16. ICC vs. Frequency for EPM7064B Devices 90 80 70 60 EPM7064B VCC = 2.5 V Room Temperature 285.7 MHz High Speed Typical ICC 50 Active (mA) 40 30 153.8 MHz Low Power 20 10 0 50 100 150 Frequency (MHz) 200 250 300 56 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Figure 17. ICC vs. Frequency for EPM7128B Devices 220 EPM7128B VCC = 2.5 V Room Temperature 238.1 MHz 200 180 160 140 Typical ICC Active (mA) 120 100 80 60 High Speed 129.9 MHz Low Power 40 20 0 50 100 150 Frequency (MHz) 200 250 Figure 18. ICC vs. Frequency for EPM7256B Devices 400 EPM7256B VCC = 2.5 V Room Temperature 350 188.7 MHz 300 High Speed 250 Typical ICC Active (mA) 200 107.5 MHz 150 Low Power 100 50 0 50 100 Frequency (MHz) 150 200 Altera Corporation 57 MAX 7000B Programmable Logic Device Data Sheet Figure 19. ICC vs. Frequency for EPM7512B Devices 700 EPM7512B 163.9 MHz VCC = 2.5 V Room Temperature 600 High Speed 500 400 Typical ICC Active (mA) 300 99.0 MHz Low Power 200 100 0 20 40 60 80 100 120 140 160 180 Frequency (MHz) 58 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Device Pin-Outs See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. Figures 20 through 29 show the package pin-out diagrams for MAX 7000B devices. Figure 20. 44-Pin PLCC/TQFP Package Pin-Out Diagram Package outlines not drawn to scale. INPUT/OE2/GCLK2 INPUT/OE2/GCLK2 INPUT/GCLRn INPUT/GCLRn INPUT/GCLK1 INPUT/GCLK1 INPUT/OE1 INPUT/OE1 GND GND VCC VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin 1 39 38 37 36 35 I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O Pin 34 6 I/O/TDI I/O I/O GND I/O I/O I/O/TMS I/O VCC I/O I/O 7 8 9 10 11 12 13 14 15 16 17 54 3 2 1 44 43 42 41 40 I/O/TDI I/O I/O GND I/O I/O I/O/TMS I/O VCC I/O I/O I/O I/O/TDO I/O I/O VCC EPM7032B EPM7064B 34 33 32 31 30 29 EPM7032B EPM7064B I/O I/O I/O/TCK I/O GND I/O 18 19 20 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND Pin 12 VCC I/O Pin 23 44-Pin PLCC 44-Pin TQFP Altera Corporation 59 MAX 7000B Programmable Logic Device Data Sheet Figure 21. 48-Pin VTQFP Package Pin-Out Diagram Package outlines not drawn to scale. INPUT/OE2/GCLK2 INPUT/GCLRN INPUT/GLK1 INPUT/OE1 GNDINT VCCINT GND 48 47 46 45 44 43 42 41 40 39 38 37 N/C I/O/TDI I/O I/O GNDIO I/O / VREFA I/O I/O/TMS I/O VCCIO1 I/O I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I/O I/O I/O I/O I/O I/O I/O GNDINT VCCINT NC I/O NC 36 35 34 33 32 31 30 29 28 27 26 25 I/O I/O/TDO I/O I/O VCCIO2 I/O I/O I/O/TCK I/O / VREFB GNDIO I/O I/O EPM7032B EPM7064B 48-Pin VTQFP Figure 22. 49-Pin Ultra FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. A1 Ball Pad Corner Indicates location of Ball A1 A B C D E EPM7032B EPM7064B EPM7128B F G 7 6 5 4 3 2 1 60 N/C I/O I/O I/O I/O Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Figure 23. 100-Pin TQFP Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin 76 EPM7064B EPM7128B EPM7256B Pin 26 Pin 51 Figure 24. 100-Pin FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. A1 Ball Pad Corner Indicates location of Ball A1 A B C D E F G EPM7064B EPM7128B EPM7256B H J K 10 9 8 7 6 5 4 3 2 1 Altera Corporation 61 MAX 7000B Programmable Logic Device Data Sheet Figure 25. 144-Pin TQFP Package Pin-Out Diagram Package outline not drawn to scale. Indicates location of Pin 1 Pin 1 Pin 109 EPM7128B EPM7256B EPM7512B Pin 37 Pin 73 Figure 26. 169-Pin Ultra FineLine BGA Pin-Out Diagram Package outline not drawn to scale. A1 Ball Pad Corner Indicates Location of Ball A1 A B C D E F G H J EPM7128AE K L M N 13 12 11 10 9 8 7 6 5 4 3 2 1 62 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Figure 27. 208-Pin PQFP Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin 157 EPM7256B EPM7512B Pin 53 Pin 105 Altera Corporation 63 MAX 7000B Programmable Logic Device Data Sheet Figure 28. 256-Pin BGA Package Pin-Out Diagram Package outline not drawn to scale. A1 Ball Pad Corner Indicates Location of Ball A1 EPM7512B A B C D E F G H J K L M N P R T U V W X Y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Figure 29. 256-Pin FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. A1 Ball Pad Corner Indicates Location of Ball A1 A B C D E F G H J EPM7128B EPM7256B EPM7512B K L M N P R T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Revision History The information contained in the MAX 7000B Programmable Logic Device Family Data Sheet version 3.4 supersedes information published in previous versions. Version 3.4 The following changes were made to the MAX 7000B Programmable Logic Device Family Data Sheet version 3.4: Updated text in the "Power Sequencing & Hot-Socketing" section.. Version 3.3 The following changes were made to the MAX 7000B Programmable Logic Device Family Data Sheet version 3.3: Updated Table 3. Added Tables 4 through 6. Altera Corporation 65 MAX 7000B Programmable Logic Device Data Sheet Version 3.2 The following changes were made to the MAX 7000B Programmable Logic Device Family Data Sheet version 3.2: Updated Note (10) and added ambient temperature (TA) information to Table 15. Version 3.1 The following changes were made to the MAX 7000B Programmable Logic Device Family Data Sheet version 3.1: Updated VIH and VIL specifications in Table 16. Updated leakage current conditions in Table 16. Version 3.0 The following changes were made to the MAX 7000B Programmable Logic Device Family Data Sheet version 3.0: Updated timing numbers in Table 1. Updated Table 16. Updated timing in Tables 18, 19, 21, 22, 24, 25, 27, 28, 30, and 31. 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com Copyright (c) 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 66 Printed on Recycled Paper. Altera Corporation |
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